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Modeling and Analyzing Yield, Burn-In and Reliability for Semiconductor Manufacturing: Overview

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Springer Handbook of Engineering Statistics

Part of the book series: Springer Handbooks ((SHB))

Abstract

The demand for proactive techniques to model yield and reliability and to deal with various infant mortality issues are growing with increased integrated circuit (IC) complexity and new technologies toward the nanoscale. This chapter provides an overview of modeling and analysis of yield and reliability with an additional burn-in step as a fundamental means for yield and reliability enhancement.

After the introduction, the second section reviews yield modeling. The notions of various yield components are introduced. The existing models, such as the Poisson model, compound Poisson models and other approaches for yield modeling, are introduced. In addition to the critical area and defect size distributions on the wafers, key factors for accurate yield modeling are also examined. This section addresses the issues in improving semiconductor yield including how clustering may affect yield.

The third section reviews reliability aspects of semiconductors such as the properties of failure mechanisms and the typical bathtub failure rate curve with an emphasis on the high rate of early failures. The issues for reliability improvement are addressed.

The fourth section discusses several issues related to burn-in. The necessity for and effects of burn-in are examined. Strategies for the level and type of burn-in are examined. The literature on optimal burn-in policy is reviewed. Often percentile residual life can be a good measure of performance in addition to the failure rate or reliability commonly used.

The fifth section introduces proactive methods of estimating semiconductor reliability from yield information using yield–reliability relation models. Time-dependent and -independent models are discussed.

The last section concludes this chapter and addresses topics for future research and development.

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Abbreviations

BIB:

burn-in board

BIR:

built-in reliability

DBI:

dynamic burn-in

DFM:

design for manufacturability

DFR:

design for reliability

DFY:

design for yield

DLBI:

die-level burn-in

DLBT:

die-level burn-in and testing

DUT:

device under test

EOS:

electrical-over-stress

ESD:

electrostatic discharge

KGD:

known good dies

PLBI:

package-level burn-in

POF:

physics-of-failure

QML:

qualified manufacturing line

SBI:

steady-state or static burn-in

TDBI:

test during burn-in

WLBI:

wafer-level burn-in

WLBT:

wafer-level burn-in and testing

WLR:

wafer-level reliability

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Tennessee, 124 Perkins Hall, 37996-2100, Knoxville, TN, USA

    Way Kuo

  2. Department of Industrial Engineering, Konkuk University, 1 Hwayang-dong, Gwangjin-gu, 143-701, Seoul, South Korea

    Kyungmee Kim

  3. Strategic Planning Office, Korea Telecom, 221 Jungja-dong, Bundang-ku, 463-711, Sungnam, Kyonggi-do, South Korea

    Taeho Kim

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  1. Way Kuo
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  2. Kyungmee Kim
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  3. Taeho Kim
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Correspondence to Way Kuo , Kyungmee Kim or Taeho Kim .

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Editors and Affiliations

  1. Department of Industrial and Systems Engineering, Rutgers the State University of New Jersey, 96 Frelinghuysen Road, 08854, Piscataway, NJ, USA

    Hoang Pham Prof.

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Kuo, W., Kim, K., Kim, T. (2006). Modeling and Analyzing Yield, Burn-In and Reliability for Semiconductor Manufacturing: Overview. In: Pham, H. (eds) Springer Handbook of Engineering Statistics. Springer Handbooks. Springer, London. https://doi.org/10.1007/978-1-84628-288-1_9

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